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LC3b Processor



The following are VHDL source files for three of the projects that were done, in collaboration with a peer Yoontae Kim, for ECE 411 Computer Architecture at University of Illinois in Fall 2004. All projects were coded with Mentor Graphics HDL Designer in VHDL.

Below are the VHDL source codes for respective functionalities


  • I wish I had taken a screenshot which would help visitors visualize how they are interconnected. Well... someday, when I get an access to HDL designer.
  • However, cpustruct.vhd will give the big picture of how the greater component blocks are connected to one another.
  • For details, grab the whole source package

lc3b_types.vhd

--
-- Component : LC3_types
--
-- Generated by System Architect version v8.4_3.7
--
--
-- Edited by Seth Herstad for ECE 312 MP1 on Aug. 20, 2003
-- Added LC3b_cc type; moved delay_mux to delay_mux2
-- Version 2.02
 
-- Edited by Seth Herstad for ECE 312 MP1 on Jan. 27, 2003
-- Removed references to arithmetic library.
-- Version 2.01
 
-- Edited by Greg Muthler for ECE 312 MP1 on January 17, 2000
-- Version 2.0
--
 
 
 
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
 
PACKAGE LC3b_types IS
-- Signal widths
	SUBTYPE LC3b_nibble IS std_logic_vector(3 downto 0);
	SUBTYPE LC3b_byte IS std_logic_vector(7 downto 0);
	SUBTYPE LC3b_word IS std_logic_vector(15 downto 0);
	SUBTYPE LC3b_aluop IS std_logic_vector(2 downto 0);
	SUBTYPE LC3b_reg IS std_logic_vector(2 downto 0);
        SUBTYPE LC3b_imm5 is std_logic_vector(4 downto 0);
	SUBTYPE LC3b_imm4 is std_logic_vector(3 downto 0);
	SUBTYPE LC3b_offset9 IS std_logic_vector(8 downto 0);
	SUBTYPE LC3b_PCoffset11 IS std_logic_vector(10 downto 0);
	SUBTYPE LC3b_index6 IS std_logic_vector(5 downto 0);
	SUBTYPE LC3b_trapvect8 IS std_logic_vector(7 downto 0);
	SUBTYPE LC3b_opcode IS std_logic_vector(3 downto 0);
        subtype LC3b_cc is std_logic_vector(2 downto 0);
 
-- Instruction definitions
	constant op_add       : LC3b_opcode := "0001";
	constant op_and       : LC3b_opcode := "0101";
	constant op_br        : LC3b_opcode := "0000";
	constant op_ret       : LC3b_opcode := "1100";	
	constant op_jmp       : LC3b_opcode := "1100";
	constant op_jsr	      : LC3b_opcode := "0100";
	constant op_jsrr      : LC3b_opcode := "0100";
	constant op_ldr       : LC3b_opcode := "0110";
	constant op_ldb       : LC3b_opcode := "0010";
	constant op_ldi	      : LC3b_opcode := "1010";
	constant op_not       : LC3b_opcode := "1001";
	constant op_str       : LC3b_opcode := "0111";
	constant op_stb	      : LC3b_opcode := "0011";
	constant op_sti       : LC3b_opcode := "1011";
	constant op_lea	      : LC3b_opcode := "1110";
	constant op_rti       : LC3b_opcode := "1000";
	constant op_shf       : LC3b_opcode := "1101";
	constant op_trap      : LC3b_opcode := "1111";
 
 
	constant alu_add      : LC3b_aluop := "000";
	constant alu_and      : LC3b_aluop := "001";
	constant alu_not      : LC3b_aluop := "010";
	constant alu_pass     : LC3b_aluop := "011";
	constant alu_pass2    : LC3b_aluop := "100";
 
-- Time delays (added for ease of use)
	constant delay_ALU : time := 15 ns;
	constant delay_ALU_ctrl : time := 5 ns;
	constant delay_adder : time := 5 ns;
	constant delay_regfile_read : time := 8 ns;
	constant delay_reg : time := 4 ns;
	constant delay_MUX2 : time := 2 ns;
        constant delay_MUX4 : time := 4 ns;
 
END LC3b_types ;

cpu_struct.vhd

-- hds header_start
--
-- VHDL Entity MP2.CPU.symbol
--
-- Created:
--          by - skim41.stdt (eesn14.ews.uiuc.edu)
--          at - 14:50:03 09/27/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
LIBRARY MP2;
USE MP2.LC3b_types.all;
 
ENTITY CPU IS
   PORT( 
      RESET_L : IN     std_logic;
      START_H : IN     std_logic;
      clk     : IN     std_logic
   );
 
-- Declarations
 
END CPU ;
 
-- hds interface_end
--
-- VHDL Architecture MP2.CPU.struct
--
-- Created:
--          by - skim41.stdt (eesn14.ews.uiuc.edu)
--          at - 14:50:04 09/27/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
LIBRARY MP2;
USE MP2.LC3b_types.all;
 
LIBRARY MP2;
 
ARCHITECTURE struct OF CPU IS
 
   -- Architecture declarations
 
   -- Internal signal declarations
   SIGNAL ADDRESS   : LC3b_word;
   SIGNAL ALUMuxSel : std_logic;
   SIGNAL ALUop     : LC3b_aluop;
   SIGNAL CheckN    : std_logic;
   SIGNAL CheckP    : std_logic;
   SIGNAL CheckZ    : std_logic;
   SIGNAL DATAIN    : LC3b_word;
   SIGNAL DATAOUT   : LC3b_word;
   SIGNAL LoadIR    : std_logic;
   SIGNAL LoadMAR   : std_logic;
   SIGNAL LoadMDR   : std_logic;
   SIGNAL LoadNZP   : std_logic;
   SIGNAL LoadPC    : std_logic;
   SIGNAL MARMuxSel : std_logic_vector(1 DOWNTO 0);
   SIGNAL MDRMuxSel : std_logic;
   SIGNAL MREAD_L   : std_logic;
   SIGNAL MRESP_H   : std_logic;
   SIGNAL MWRITEH_L : std_logic;
   SIGNAL MWRITEL_L : std_logic;
   SIGNAL Opcode    : LC3b_opcode;
   SIGNAL PCMuxSel  : std_logic_vector(1 DOWNTO 0);
   SIGNAL RFMuxSel  : std_logic_vector(1 DOWNTO 0);
   SIGNAL RegWrite  : std_logic;
   SIGNAL StoreSR   : std_logic;
   SIGNAL bit11     : std_logic;
   SIGNAL n         : std_logic;
   SIGNAL p         : std_logic;
   SIGNAL z         : std_logic;
 
 
   -- Component Declarations
   COMPONENT Control
   PORT (
      CheckN    : IN     std_logic ;
      CheckP    : IN     std_logic ;
      CheckZ    : IN     std_logic ;
      MRESP_H   : IN     std_logic ;
      Opcode    : IN     LC3b_opcode ;
      RESET_L   : IN     std_logic ;
      START_H   : IN     std_logic ;
      bit11     : IN     std_logic ;
      clk       : IN     std_logic ;
      n         : IN     std_logic ;
      p         : IN     std_logic ;
      z         : IN     std_logic ;
      ALUMuxSel : OUT    std_logic ;
      ALUop     : OUT    LC3b_aluop ;
      LoadIR    : OUT    std_logic ;
      LoadMAR   : OUT    std_logic ;
      LoadMDR   : OUT    std_logic ;
      LoadNZP   : OUT    std_logic ;
      LoadPC    : OUT    std_logic ;
      MARMuxSel : OUT    std_logic_vector (1 DOWNTO 0);
      MDRMuxSel : OUT    std_logic ;
      MREAD_L   : OUT    std_logic ;
      MWRITEH_L : OUT    std_logic ;
      MWRITEL_L : OUT    std_logic ;
      PCMuxSel  : OUT    std_logic_vector (1 DOWNTO 0);
      RFMuxSel  : OUT    std_logic_vector (1 DOWNTO 0);
      RegWrite  : OUT    std_logic ;
      StoreSR   : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT Datapath
   PORT (
      ALUMuxSel : IN     std_logic ;
      ALUop     : IN     LC3b_aluop ;
      DATAIN    : IN     LC3b_word ;
      LoadIR    : IN     std_logic ;
      LoadMAR   : IN     std_logic ;
      LoadMDR   : IN     std_logic ;
      LoadNZP   : IN     std_logic ;
      LoadPC    : IN     std_logic ;
      MARMuxSel : IN     std_logic_vector (1 DOWNTO 0);
      MDRMuxSel : IN     std_logic ;
      PCMuxSel  : IN     std_logic_vector (1 DOWNTO 0);
      RESET_L   : IN     std_logic ;
      RFMuxSel  : IN     std_logic_vector (1 DOWNTO 0);
      RegWrite  : IN     std_logic ;
      StoreSR   : IN     std_logic ;
      clk       : IN     std_logic ;
      ADDRESS   : OUT    LC3b_word ;
      CheckN    : OUT    std_logic ;
      CheckP    : OUT    std_logic ;
      CheckZ    : OUT    std_logic ;
      DATAOUT   : OUT    LC3b_word ;
      Opcode    : OUT    LC3b_opcode ;
      bit11     : OUT    std_logic ;
      n         : OUT    std_logic ;
      p         : OUT    std_logic ;
      z         : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT Memory
   PORT (
      ADDRESS   : IN     LC3b_word ;
      DATAOUT   : IN     LC3b_word ;
      MREAD_L   : IN     std_logic ;
      MWRITEH_L : IN     std_logic ;
      MWRITEL_L : IN     std_logic ;
      RESET_L   : IN     std_logic ;
      clk       : IN     std_logic ;
      DATAIN    : OUT    LC3b_word ;
      MRESP_H   : OUT    std_logic 
   );
   END COMPONENT;
 
   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : Control USE ENTITY MP2.Control;
   FOR ALL : Datapath USE ENTITY MP2.Datapath;
   FOR ALL : Memory USE ENTITY MP2.Memory;
   -- pragma synthesis_on
 
 
BEGIN
   -- Instance port mappings.
   I0 : Control
      PORT MAP (
         CheckN    => CheckN,
         CheckP    => CheckP,
         CheckZ    => CheckZ,
         MRESP_H   => MRESP_H,
         Opcode    => Opcode,
         RESET_L   => RESET_L,
         START_H   => START_H,
         bit11     => bit11,
         clk       => clk,
         n         => n,
         p         => p,
         z         => z,
         ALUMuxSel => ALUMuxSel,
         ALUop     => ALUop,
         LoadIR    => LoadIR,
         LoadMAR   => LoadMAR,
         LoadMDR   => LoadMDR,
         LoadNZP   => LoadNZP,
         LoadPC    => LoadPC,
         MARMuxSel => MARMuxSel,
         MDRMuxSel => MDRMuxSel,
         MREAD_L   => MREAD_L,
         MWRITEH_L => MWRITEH_L,
         MWRITEL_L => MWRITEL_L,
         PCMuxSel  => PCMuxSel,
         RFMuxSel  => RFMuxSel,
         RegWrite  => RegWrite,
         StoreSR   => StoreSR
      );
   I2 : Datapath
      PORT MAP (
         ALUMuxSel => ALUMuxSel,
         ALUop     => ALUop,
         DATAIN    => DATAIN,
         LoadIR    => LoadIR,
         LoadMAR   => LoadMAR,
         LoadMDR   => LoadMDR,
         LoadNZP   => LoadNZP,
         LoadPC    => LoadPC,
         MARMuxSel => MARMuxSel,
         MDRMuxSel => MDRMuxSel,
         PCMuxSel  => PCMuxSel,
         RESET_L   => RESET_L,
         RFMuxSel  => RFMuxSel,
         RegWrite  => RegWrite,
         StoreSR   => StoreSR,
         clk       => clk,
         ADDRESS   => ADDRESS,
         CheckN    => CheckN,
         CheckP    => CheckP,
         CheckZ    => CheckZ,
         DATAOUT   => DATAOUT,
         Opcode    => Opcode,
         bit11     => bit11,
         n         => n,
         p         => p,
         z         => z
      );
   I1 : Memory
      PORT MAP (
         ADDRESS   => ADDRESS,
         DATAOUT   => DATAOUT,
         MREAD_L   => MREAD_L,
         MWRITEH_L => MWRITEH_L,
         MWRITEL_L => MWRITEL_L,
         RESET_L   => RESET_L,
         clk       => clk,
         DATAIN    => DATAIN,
         MRESP_H   => MRESP_H
      );
 
END struct;

control_fsm.vhd

-- hds header_start
--
-- VHDL Entity MP2.Control.interface
--
-- Created:
--          by - skim41.stdt (eesn14.ews.uiuc.edu)
--          at - 14:58:53 09/27/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
LIBRARY MP2;
USE MP2.LC3b_types.all;
 
ENTITY Control IS
   PORT( 
      CheckN    : IN     std_logic;
      CheckP    : IN     std_logic;
      CheckZ    : IN     std_logic;
      MRESP_H   : IN     std_logic;
      Opcode    : IN     LC3b_opcode;
      RESET_L   : IN     std_logic;
      START_H   : IN     std_logic;
      bit11     : IN     std_logic;
      clk       : IN     std_logic;
      n         : IN     std_logic;
      p         : IN     std_logic;
      z         : IN     std_logic;
      ALUMuxSel : OUT    std_logic;
      ALUop     : OUT    LC3b_aluop;
      LoadIR    : OUT    std_logic;
      LoadMAR   : OUT    std_logic;
      LoadMDR   : OUT    std_logic;
      LoadNZP   : OUT    std_logic;
      LoadPC    : OUT    std_logic;
      MARMuxSel : OUT    std_logic_vector (1 DOWNTO 0);
      MDRMuxSel : OUT    std_logic;
      MREAD_L   : OUT    std_logic;
      MWRITEH_L : OUT    std_logic;
      MWRITEL_L : OUT    std_logic;
      PCMuxSel  : OUT    std_logic_vector (1 DOWNTO 0);
      RFMuxSel  : OUT    std_logic_vector (1 DOWNTO 0);
      RegWrite  : OUT    std_logic;
      StoreSR   : OUT    std_logic
   );
 
-- Declarations
 
END Control ;
 
-- hds interface_end
--
-- VHDL Architecture MP2.Control.fsm
--
-- Created:
--          by - skim41.stdt (eesn14.ews.uiuc.edu)
--          at - 14:58:53 09/27/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2;
USE MP2.LC3b_types.all;
 
ARCHITECTURE fsm OF Control IS
 
   -- Architecture Declarations
   TYPE STATE_TYPE IS (
      Reset,
      Decode,
      L_NOT,
      L_AND,
      ADD,
      BR1,
      BR2,
      LEA1,
      LEA2,
      s2,
      s3,
      s4,
      s5,
      s6,
      s7,
      s0,
      IF1,
      IF2,
      IF3,
      CalcAddr,
      ST1,
      ST2,
      LD1,
      LD2,
      CalcAddr2,
      LD7,
      ST6,
      LD8,
      s1,
      ST4,
      CalcAddr1,
      LD4,
      LD6,
      LD3,
      LD5
   );
 
   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state" ;
 
 
   -- Declare current and next state signals
   SIGNAL current_state : STATE_TYPE ;
   SIGNAL next_state : STATE_TYPE ;
 
BEGIN
 
   ----------------------------------------------------------------------------
   clocked : PROCESS(
      clk,
      RESET_L
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (RESET_L = '0') THEN
         current_state <= Reset;
         -- Reset Values
      ELSIF (clk'EVENT AND clk = '1') THEN
         current_state <= next_state;
         -- Default Assignment To Internals
 
      END IF;
 
   END PROCESS clocked;
 
   ----------------------------------------------------------------------------
   nextstate : PROCESS (
      CheckN,
      CheckP,
      CheckZ,
      MRESP_H,
      Opcode,
      START_H,
      bit11,
      current_state,
      n,
      p,
      z
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE current_state IS
      WHEN Reset =>
         IF (START_H = '1') THEN
            next_state <= IF1;
         ELSE
            next_state <= Reset;
         END IF;
      WHEN Decode =>
         IF (Opcode = op_add) THEN
            next_state <= ADD;
         ELSIF (Opcode = op_and) THEN
            next_state <= L_AND;
         ELSIF (Opcode = op_not) THEN
            next_state <= L_NOT;
         ELSIF ((Opcode = op_ldr) OR 
         (Opcode = op_str)) THEN
            next_state <= CalcAddr;
         ELSIF ((Opcode = op_ldb) OR
         (Opcode = op_stb)) THEN
            next_state <= CalcAddr2;
         ELSIF ((Opcode = op_ldi) OR
         (Opcode = op_sti)) THEN
            next_state <= CalcAddr1;
         ELSIF (Opcode = op_br) THEN
            next_state <= BR1;
         ELSIF (Opcode = op_lea) THEN
            next_state <= LEA1;
         ELSIF ((opcode = op_jmp) OR (opcode = op_ret)) THEN
            next_state <= s2;
         ELSIF ((opcode = op_jsr) OR (opcode = op_jsrr)
         OR (opcode = op_trap)) THEN
            next_state <= s4;
         ELSIF (opcode = op_shf) THEN
            next_state <= s0;
         ELSE
            next_state <= IF1;
         END IF;
      WHEN L_NOT =>
            next_state <= IF1;
      WHEN L_AND =>
            next_state <= IF1;
      WHEN ADD =>
            next_state <= IF1;
      WHEN BR1 =>
         IF (((n AND CheckN) OR
         (p AND CheckP) OR
         (z AND CheckZ)) = '1') THEN
            next_state <= BR2;
         ELSE
            next_state <= IF1;
         END IF;
      WHEN BR2 =>
            next_state <= IF1;
      WHEN LEA1 =>
            next_state <= LEA2;
      WHEN LEA2 =>
            next_state <= IF1;
      WHEN s2 =>
            next_state <= s3;
      WHEN s3 =>
            next_state <= IF1;
      WHEN s4 =>
         IF ((opcode = op_jsr) and (Bit11 = '1')) THEN
            next_state <= s6;
         ELSIF ((opcode = op_jsrr) and (Bit11 = '0')) THEN
            next_state <= s5;
         ELSIF (Opcode = op_trap) THEN
            next_state <= s7;
         ELSE
            next_state <= s4;
         END IF;
      WHEN s5 =>
            next_state <= IF1;
      WHEN s6 =>
            next_state <= IF1;
      WHEN s7 =>
            next_state <= IF1;
      WHEN s0 =>
            next_state <= IF1;
      WHEN IF1 =>
            next_state <= IF2;
      WHEN IF2 =>
         IF (MRESP_H = '1') THEN
            next_state <= IF3;
         ELSE
            next_state <= IF2;
         END IF;
      WHEN IF3 =>
            next_state <= Decode;
      WHEN CalcAddr =>
         IF (Opcode = op_str) THEN
            next_state <= ST1;
         ELSIF (Opcode = op_ldr) THEN
            next_state <= LD1;
         ELSE
            next_state <= CalcAddr;
         END IF;
      WHEN ST1 =>
            next_state <= ST2;
      WHEN ST2 =>
         IF (MRESP_H = '1') THEN
            next_state <= IF1;
         ELSE
            next_state <= ST2;
         END IF;
      WHEN LD1 =>
         IF (MRESP_H = '1') THEN
            next_state <= LD2;
         ELSE
            next_state <= LD1;
         END IF;
      WHEN LD2 =>
            next_state <= IF1;
      WHEN CalcAddr2 =>
         IF (Opcode = op_ldb) THEN
            next_state <= LD7;
         ELSIF (Opcode = op_stb) THEN
            next_state <= ST6;
         ELSE
            next_state <= CalcAddr2;
         END IF;
      WHEN LD7 =>
         IF (MRESP_H = '1') THEN
            next_state <= LD8;
         ELSE
            next_state <= LD7;
         END IF;
      WHEN ST6 =>
         IF (MRESP_H = '1') THEN
            next_state <= IF1;
         ELSE
            next_state <= ST6;
         END IF;
      WHEN LD8 =>
            next_state <= IF1;
      WHEN s1 =>
            next_state <= ST4;
      WHEN ST4 =>
         IF (MRESP_H = '1') THEN
            next_state <= IF1;
         ELSE
            next_state <= ST4;
         END IF;
      WHEN CalcAddr1 =>
            next_state <= LD3;
      WHEN LD4 =>
         IF (Opcode = op_ldi) THEN
            next_state <= LD5;
         ELSIF (Opcode = op_sti) THEN
            next_state <= s1;
         ELSE
            next_state <= LD4;
         END IF;
      WHEN LD6 =>
            next_state <= IF1;
      WHEN LD3 =>
         IF (MRESP_H = '1') THEN
            next_state <= LD4;
         ELSE
            next_state <= LD3;
         END IF;
      WHEN LD5 =>
         IF (MRESP_H = '1') THEN
            next_state <= LD6;
         ELSE
            next_state <= LD5;
         END IF;
      WHEN OTHERS =>
         next_state <= Reset;
      END CASE;
 
   END PROCESS nextstate;
 
   ----------------------------------------------------------------------------
   output : PROCESS (
      current_state
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      ALUMuxSel <= '0';
      ALUop <= "000";
      LoadIR <= '0';
      LoadMAR <= '0';
      LoadMDR <= '0';
      LoadNZP <= '0';
      LoadPC <= '0';
      MARMuxSel <= "00";
      MDRMuxSel <= '0';
      MREAD_L <= '1';
      MWRITEH_L <= '1';
      MWRITEL_L <= '1';
      PCMuxSel <= "00";
      RFMuxSel <= "00";
      RegWrite <= '0';
      StoreSR <= '1';
      -- Default Assignment To Internals
 
      -- Combined Actions
      CASE current_state IS
      WHEN L_NOT =>
         ALUop <= alu_not;
         RegWrite <= '1';
         LoadNZP <= '1';
         RFMuxSel <= "01";
      WHEN L_AND =>
         ALUop <= alu_and;
         RegWrite <= '1';
         LoadNZP <= '1';
         RFMuxSel <= "01";
      WHEN ADD =>
         ALUop <= alu_add;
         RegWrite <= '1';
         LoadNZP <= '1';
         RFMuxSel <= "01";
      WHEN BR2 =>
         PCMuxSel <= "01";
         LoadPC <= '1';
      WHEN LEA1 =>
         RFMuxSel <= "11";
         RegWrite <= '1';
      WHEN LEA2 =>
         LoadNZP <= '1';
      WHEN s2 =>
         StoreSR <= '1';
         RegWrite <= '0';
         ALUop <= alu_pass;
         MARMuxSel <= "01";
         loadMAR <= '1';
      WHEN s3 =>
         aluop <= alu_pass;
         MDRMuxSel <= '1';
         LoadMDR <= '1';
         LoadIR <= '1';
         PCMuxSel <= "11";
         LoadPC <= '1';
      WHEN s4 =>
         RFMuxSel <= "10";
         RegWrite <= '1';
      WHEN s5 =>
         StoreSR <= '1';
         ALUop <= alu_pass;
         MDRMuxSel <= '1';
         LoadMDR <= '1';
         LoadIR <= '1';
         PCMuxSel <= "11";
         LoadPC <= '1';
      WHEN s6 =>
         PCMuxSel <= "01";
         LoadPC <= '1';
      WHEN s7 =>
         ALUMuxSel <= '1';
         ALUop <= alu_pass2;
         MARMuxSel <= "01";
         LoadMAR <= '1';
         MDRMuxSel <= '1';
         LoadMDR <= '1';
         LoadIR <= '1';
         PCMuxSel <= "11";
         LoadPC <= '1';
      WHEN s0 =>
         StoreSR <= '1';
         ALUop <= alu_pass;
         RFMuxSel <= "01";
         LoadNZP <= '1';
         RegWrite <= '1';
      WHEN IF1 =>
         LoadMAR <= '1';
         LoadPC <= '1';
      WHEN IF2 =>
         LoadMDR <= '1';
         MREAD_L <= '0' after 6 ns;
      WHEN IF3 =>
         LoadIR <= '1';
      WHEN CalcAddr =>
         ALUMuxSel <= '1';
         ALUop <= alu_add;
         MARMuxSel <= "01";
         LoadMAR <= '1';
      WHEN ST1 =>
         StoreSR <= '0';
         ALUop <= alu_pass;
         LoadMDR <= '1';
         MDRMuxSel <= '1';
      WHEN ST2 =>
         MWRITEH_L <= '0' after 6 ns;
         MWRITEL_L <= '0' after 6 ns;
      WHEN LD1 =>
         MDRMuxSel <= '0';
         LoadMDR <= '1';
         MREAD_L <= '0' after 6 ns;
      WHEN LD2 =>
         RegWrite <= '1';
         LoadNZP <= '1';
      WHEN CalcAddr2 =>
         StoreSR <= '1';
         ALUMuxSel <= '1';
         ALUop <= alu_add;
         MARMuxSel <= "01";
         LoadMAR <= '1';
      WHEN LD7 =>
         MDRMuxSel <= '0';
         LoadMDR <= '1';
         RFMuxSel <= "00";
         MREAD_L <= '0' after 6 ns;
      WHEN ST6 =>
         StoreSR <= '0';
         ALUop <= alu_pass;
         MDRMuxSel <= '1';
         LoadMDR <= '1';
         MWRITEL_L <= '0' after 6 ns;
      WHEN LD8 =>
         RegWrite <= '1';
         LoadNZP <= '1';
      WHEN s1 =>
         StoreSR <= '0';
         ALUop <= alu_pass;
         MDRMuxSel <= '1';
         LoadMDR <= '1';
      WHEN ST4 =>
         MWRITEH_L <= '0' after 8 ns;
         MWRITEL_L <= '0' after 8 ns;
      WHEN CalcAddr1 =>
         StoreSR <= '1';
         ALUMuxSel <= '1';
         ALUop <= alu_add;
         MARMuxSel <= "01";
         LoadMAR <= '1';
      WHEN LD4 =>
         MDRMuxSel <= '0';
         LoadMDR <= '1';
         MARMuxSel <= "10";
         LoadMAR <= '1';
      WHEN LD6 =>
         RFMuxSel <= "00";
         RegWrite <= '1';
         LoadNZP <= '1';
      WHEN LD3 =>
         MDRMuxSel <= '0';
         LoadMDR <= '1';
         MREAD_L <= '0' after 6 ns;
      WHEN LD5 =>
         LoadMDR <= '1';
         MDRMuxSel <= '0';
         MREAD_L <= '0' after 6 ns;
      WHEN OTHERS =>
         NULL;
      END CASE;
 
   END PROCESS output;
 
   -- Concurrent Statements
 
END fsm;

cache_controller_fsm.vhd

-- hds header_start
--
-- VHDL Entity MP2_2.Cache_Controller.interface
--
-- Created:
--          by - skim41.stdt (eesn21.ews.uiuc.edu)
--          at - 16:14:47 10/18/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2_2;
USE MP2_2.LC3b_types.all;
 
ENTITY Cache_Controller IS
   PORT( 
      Address       : IN     LC3b_word;
      Clk           : IN     std_logic;
      Data_cacheout : IN     LC3b_CacheLine64;
      Data_wordout  : IN     LC3b_word;
      Dataout       : IN     LC3b_word;
      MREAD_L       : IN     std_logic;
      MWRITEH_L     : IN     std_logic;
      MWRITEL_L     : IN     std_logic;
      PMRESP_H      : IN     std_logic;
      Reset_L       : IN     std_logic;
      lrusel        : IN     std_logic;
      tag0match     : IN     std_logic;
      tag1match     : IN     std_logic;
      DataIn        : OUT    LC3b_word;
      LineSel       : OUT    std_logic;
      MRESP_H       : OUT    std_logic;
      PMAddress     : OUT    LC3b_word;
      PMDataOut     : OUT    LC3b_CacheLine64;
      PMREAD_L      : OUT    std_logic;
      PMWRITE_L     : OUT    std_logic;
      WriteEn0      : OUT    std_logic;
      WriteEn1      : OUT    std_logic;
      index         : OUT    LC3b_index4;
      lruload       : OUT    std_logic;
      lruupdate     : OUT    std_logic;
      offset        : OUT    LC3b_offset3;
      tag           : OUT    LC3b_tag9
   );
 
-- Declarations
 
END Cache_Controller ;
 
-- hds interface_end
--
-- VHDL Architecture MP2_2.Cache_Controller.fsm
--
-- Created:
--          by - skim41.stdt (eesn21.ews.uiuc.edu)
--          at - 16:14:47 10/18/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2_2;
USE MP2_2.LC3b_types.all;
 
ARCHITECTURE fsm OF Cache_Controller IS
 
   -- Architecture Declarations
   TYPE STATE_TYPE IS (
      Read_hit,
      Read_miss,
      Write_hit2,
      Write_hit1,
      Write_hit3,
      Reset,
      UpdateData,
      Write_miss1,
      Write_miss2,
      Write_miss3,
      UpdateLRU
   );
 
   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state" ;
 
 
   -- Declare current and next state signals
   SIGNAL current_state : STATE_TYPE ;
   SIGNAL next_state : STATE_TYPE ;
 
BEGIN
 
   ----------------------------------------------------------------------------
   clocked : PROCESS(
      Clk,
      Reset_L
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (Reset_L = '0') THEN
         current_state <= Reset;
         -- Reset Values
      ELSIF (Clk'EVENT AND Clk = '1') THEN
         current_state <= next_state;
         -- Default Assignment To Internals
 
      END IF;
 
   END PROCESS clocked;
 
   ----------------------------------------------------------------------------
   nextstate : PROCESS (
      MREAD_L,
      MWRITEH_L,
      MWRITEL_L,
      PMRESP_H,
      current_state,
      tag0match,
      tag1match
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE current_state IS
      WHEN Read_hit =>
         IF ((tag0match = '0') and (tag1match = '0')) THEN
            next_state <= Read_miss;
         ELSIF ((MWRITEL_L = '0') AND (MWRITEH_L = '0')) THEN
            next_state <= Write_hit1;
         ELSIF (MWRITEL_L = '0') THEN
            next_state <= Write_hit2;
         ELSIF (MWRITEH_L = '0') THEN
            next_state <= Write_hit3;
         ELSE
            next_state <= Read_hit;
         END IF;
      WHEN Read_miss =>
         IF ((MWRITEL_L = '0') AND (MWRITEH_L = '0')) THEN
            next_state <= Write_miss1;
         ELSIF (MWRITEL_L = '0') THEN
            next_state <= Write_miss2;
         ELSIF (MWRITEH_L = '0') THEN
            next_state <= Write_miss3;
         ELSIF (MREAD_L='0' and PMRESP_H = '1') THEN
            next_state <= UpdateData;
         ELSE
            next_state <= Read_miss;
         END IF;
      WHEN Write_hit2 =>
         IF (PMRESP_H = '1') THEN
            next_state <= UpdateData;
         ELSE
            next_state <= Write_hit2;
         END IF;
      WHEN Write_hit1 =>
         IF (PMRESP_H = '1') THEN
            next_state <= UpdateData;
         ELSE
            next_state <= Write_hit1;
         END IF;
      WHEN Write_hit3 =>
         IF (PMRESP_H = '1') THEN
            next_state <= UpdateData;
         ELSE
            next_state <= Write_hit3;
         END IF;
      WHEN Reset =>
            next_state <= Read_hit;
      WHEN UpdateData =>
            next_state <= UpdateLRU;
      WHEN Write_miss1 =>
         IF (PMRESP_H = '1') THEN
            next_state <= UpdateData;
         ELSE
            next_state <= Write_miss1;
         END IF;
      WHEN Write_miss2 =>
         IF (PMRESP_H = '1') THEN
            next_state <= UpdateData;
         ELSE
            next_state <= Write_miss2;
         END IF;
      WHEN Write_miss3 =>
         IF (PMRESP_H = '1') THEN
            next_state <= UpdateData;
         ELSE
            next_state <= Write_miss3;
         END IF;
      WHEN UpdateLRU =>
            next_state <= Read_hit;
      WHEN OTHERS =>
         next_state <= Reset;
      END CASE;
 
   END PROCESS nextstate;
 
   ----------------------------------------------------------------------------
   output : PROCESS (
      Address,
      Data_cacheout,
      Data_wordout,
      Dataout,
      MWRITEH_L,
      MWRITEL_L,
      current_state,
      lrusel,
      tag0match,
      tag1match
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      DataIn <= Data_wordout;
      LineSel <= '0';
      MRESP_H <= '0';
      PMAddress <= Address;
      PMDataOut <= Data_cacheout;
      PMREAD_L <= '1';
      PMWRITE_L <= '1';
      WriteEn0 <= '0';
      WriteEn1 <= '0';
      index <= Address(6 downto 3);
      lruload <= '0';
      lruupdate <= '1';
      offset <= Address(2 downto 0);
      tag <= Address(15 downto 7);
      -- Default Assignment To Internals
 
      -- Combined Actions
      CASE current_state IS
      WHEN Read_hit =>
         DataIn <= Data_wordout;
         if (tag0match = '1') then
            LineSel <= '0';
            lruupdate <= '0';
         elsif (tag1match = '1') then
            LineSel <= '1';
            lruupdate <= '1';
         end if;
         IF ((tag0match = '0') and (tag1match = '0')) THEN
         ELSIF ((MWRITEL_L = '0') AND (MWRITEH_L = '0')) THEN
            LRUload <= '0';
         ELSIF (MWRITEL_L = '0') THEN
            LRUload <= '0';
         ELSIF (MWRITEH_L = '0') THEN
            LRUload <= '0';
         ELSE
            MRESP_H <= '1';
         END IF;
      WHEN Read_miss =>
         pmread_L <= '0';
      WHEN Write_hit2 =>
         case address(2 downto 0) is
            when "000" =>
               PMDataOut <= (Data_cacheout(63 downto 8) &amp; DataOut(7 downto 0));      
            when "010" =>
               PMDataOut <= (Data_cacheout(63 downto 24) &amp; DataOut(7 downto 0) &amp; Data_cacheout(15 downto 0));      
            when "011" =>
               PMDataOut <= (Data_cacheout(63 downto 32) &amp; DataOut(7 downto 0) &amp; Data_cacheout(23 downto 0));      
            when "100" =>
               PMDataOut <= (Data_cacheout(63 downto 40) &amp; DataOut(7 downto 0) &amp; Data_cacheout(31 downto 0));      
            when "110" =>
               PMDataOut <= (Data_cacheout(63 downto 56) &amp; DataOut(7 downto 0) &amp; Data_cacheout(47 downto 0)); 
            when Others =>
               PMDataOut <= Data_cacheout;       
         end case;
         PMWRITE_L <= '0';
      WHEN Write_hit1 =>
         case address(2 downto 0) is
            when "000" =>
               PMDataOut <= (Data_cacheout(63 downto 16) &amp; DataOut);      
            when "010" =>
               PMDataOut <= (Data_cacheout(63 downto 32) &amp; DataOut &amp; Data_cacheout(15 downto 0));      
            when "100" =>
               PMDataOut <= (Data_cacheout(63 downto 48) &amp; DataOut &amp; Data_cacheout(31 downto 0));      
             when "101" =>
               PMDataOut <= (Data_cacheout(63 downto 56) &amp; DataOut &amp; Data_cacheout(39 downto 0));       
           when "110" =>
               PMDataOut <= (DataOut &amp; Data_cacheout(47 downto 0));      
            when Others =>
               PMDataOut <= Data_cacheout;  
         end case;
         PMWRITE_L <= '0';
      WHEN Write_hit3 =>
         case address(2 downto 0) is
            when "000" =>
               PMDataOut <= (Data_cacheout(63 downto 16) &amp; DataOut(15 downto 8) &amp; Data_cacheout(7 downto 0));      
            when "010" =>
               PMDataOut <= (Data_cacheout(63 downto 32) &amp; DataOut(15 downto 8) &amp; Data_cacheout(23 downto 0));      
            when "100" =>
               PMDataOut <= (Data_cacheout(63 downto 48) &amp; DataOut(15 downto 8) &amp; Data_cacheout(39 downto 0));      
            when "110" =>
               PMDataOut <= (DataOut(15 downto 8) &amp; Data_cacheout(55 downto 0)); 
            when Others =>
               PMDataOut <= Data_cacheout;       
         end case;
         PMWRITE_L <= '0';
      WHEN UpdateData =>
         if (lrusel = '1') then
            WriteEn0 <= '1';
         else
            WriteEn1 <= '1';
         end if;
      WHEN Write_miss1 =>
         case address(2 downto 0) is
            when "000" =>
               PMDataOut <= (Data_cacheout(63 downto 16) &amp; DataOut);      
            when "010" =>
               PMDataOut <= (Data_cacheout(63 downto 32) &amp; DataOut &amp; Data_cacheout(15 downto 0));      
            when "100" =>
               PMDataOut <= (Data_cacheout(63 downto 48) &amp; DataOut &amp; Data_cacheout(31 downto 0));      
            when "101" =>
               PMDataOut <= (Data_cacheout(63 downto 56) &amp; DataOut &amp; Data_cacheout(39 downto 0));
            when "110" =>
               PMDataOut <= (DataOut &amp; Data_cacheout(47 downto 0));   
            when Others =>
               PMDataOut <= Data_cacheout;   
         end case;
         PMWRITE_L <= '0';
      WHEN Write_miss2 =>
         case address(2 downto 0) is
            when "000" =>
               PMDataOut <= (Data_cacheout(63 downto 8) &amp; DataOut(7 downto 0));      
            when "010" =>
               PMDataOut <= (Data_cacheout(63 downto 24) &amp; DataOut(7 downto 0) &amp; Data_cacheout(15 downto 0));      
            when "100" =>
               PMDataOut <= (Data_cacheout(63 downto 40) &amp; DataOut(7 downto 0) &amp; Data_cacheout(31 downto 0));      
            when "110" =>
               PMDataOut <= (Data_cacheout(63 downto 56) &amp; DataOut(7 downto 0) &amp; Data_cacheout(47 downto 0));   
            when Others =>
               PMDataOut <= Data_cacheout;   
         end case;
         PMWRITE_L <= '0';
      WHEN Write_miss3 =>
         case address(2 downto 0) is
            when "000" =>
               PMDataOut <= (Data_cacheout(63 downto 8) &amp; DataOut(7 downto 0));      
            when "010" =>
               PMDataOut <= (Data_cacheout(63 downto 24) &amp; DataOut(7 downto 0) &amp; Data_cacheout(15 downto 0));      
            when "100" =>
               PMDataOut <= (Data_cacheout(63 downto 40) &amp; DataOut(7 downto 0) &amp; Data_cacheout(31 downto 0));      
            when "110" =>
               PMDataOut <= (Data_cacheout(63 downto 56) &amp; DataOut(7 downto 0) &amp; Data_cacheout(47 downto 0));    
            when Others =>
               PMDataOut <= Data_cacheout;  
         end case;
         PMWRITE_L <= '0';
      WHEN UpdateLRU =>
         if (lrusel = '1') then
           WriteEn0 <= '0';
           lruupdate <= '0';
         elsif (lrusel = '0') then
           WriteEn1 <= '0';
           lruupdate <= '1';
         end if;
         lruload <= '1';
         MRESP_H <= '1';
      WHEN OTHERS =>
         NULL;
      END CASE;
 
   END PROCESS output;
 
   -- Concurrent Statements
 
END fsm;

dram_untitled.vhd

-- hds header_start
--
-- VHDL Architecture MP2_2.DRAM.untitled
--
-- Created:
--          by - skim41.stdt (eesn20.ews.uiuc.edu)
--          at - 23:54:28 10/14/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2_2;
USE MP2_2.LC3b_types.all;
 
ENTITY DRAM IS
   PORT( 
      Clk       : IN     std_logic;
      PMAddress : IN     LC3b_word;
      PMDataOut : IN     LC3b_CacheLine64;
      PMREAD_L  : IN     std_logic;
      PMWRITE_L : IN     std_logic;
      Reset_L   : IN     std_logic;
      PMDataIn  : OUT    LC3b_CacheLine64;
      PMRESP_H  : OUT    std_logic
   );
 
-- Declarations
 
END DRAM ;
 
-- hds interface_end
ARCHITECTURE untitled OF DRAM IS
BEGIN
 
   -------------------------------------------------------------------
   vhdl_memory : PROCESS (RESET_L, PMREAD_L, PMWRITE_L) 
   -------------------------------------------------------------------
     TYPE memory_array IS	array (0 to 8192) of LC3b_byte;
     VARIABLE mem : memory_array;
     VARIABLE int_address : integer;
   BEGIN
     int_address := to_integer(unsigned(PMADDRESS(12 downto 3)) * 8);
 
     IF Reset_L = '0' then
       PMRESP_H <= '0';
 
-- Insert Memory vectors here
  -- Example: mem(0) := To_stdlogicvector(X"00");
 
 
	mem(0) := To_stdlogicvector(X"6E");
	mem(1) := To_stdlogicvector(X"E0");
        .
        .
        .
	mem(524) := To_stdlogicvector(X"88");
	mem(525) := To_stdlogicvector(X"88");
 
 
 
-- Stop.
 
     ELSE
       IF ((int_address >= 0) and (int_address <= 8192)) THEN
         IF (PMREAD_L = '0' and PMWRITE_L = '1') THEN
             PMDATAIN(7 downto 0) <= mem(int_address) after 500 ns;            
             PMDATAIN(15 downto 8) <= mem(int_address + 1) after 500 ns;
             PMDATAIN(23 downto 16) <= mem(int_address + 2) after 500 ns;
             PMDATAIN(31 downto 24) <= mem(int_address + 3) after 500 ns;
             PMDATAIN(39 downto 32) <= mem(int_address + 4) after 500 ns;            
             PMDATAIN(47 downto 40) <= mem(int_address + 5) after 500 ns;
             PMDATAIN(55 downto 48) <= mem(int_address + 6) after 500 ns;
             PMDATAIN(63 downto 56) <= mem(int_address + 7) after 500 ns;
 
             PMRESP_H <= '1' after 500 ns, '0' after 550 ns;
             -- You may change the '530ns' above to '500 + your clock cycle';
 
         ELSIF (PMWRITE_L = '0' and PMREAD_L = '1') THEN
 
             mem(int_address) := PMDATAOUT(7 downto 0);
             mem(int_address + 1) := PMDATAOUT(15 downto 8);
             mem(int_address + 2) := PMDATAOUT(23 downto 16);
             mem(int_address + 3) := PMDATAOUT(31 downto 24);
             mem(int_address + 4) := PMDATAOUT(39 downto 32);
             mem(int_address + 5) := PMDATAOUT(47 downto 40);
             mem(int_address + 6) := PMDATAOUT(55 downto 48);
             mem(int_address + 7) := PMDATAOUT(63 downto 56);
 
 
             PMRESP_H <= '1' after 500 ns, '0' after 550 ns;             
             -- You may change the '530ns' above to '500 + your clock cycle';
 
         ELSE
           ASSERT false 
             REPORT "Memory Write"
             SEVERITY note;
         END IF;
       ELSE
         ASSERT false
           REPORT "Invalid address"
           SEVERITY warning;
       END IF;
     END IF;
   END PROCESS vhdl_memory;
 
 
END untitled;

comparator1_untitled.vhd

-- hds header_start
--
-- VHDL Architecture MP2_2.Comparator1.untitled
--
-- Created:
--          by - skim41.stdt (glsn46.ews.uiuc.edu)
--          at - 16:39:56 10/15/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2_2;
USE MP2_2.LC3b_types.all;
 
ENTITY Comparator1 IS
   PORT( 
      Clk       : IN     std_logic;
      tag       : IN     LC3b_tag9;
      tag0_out  : IN     LC3b_tag9;
      Comp_Out1 : OUT    std_logic
   );
 
-- Declarations
 
END Comparator1 ;
 
-- hds interface_end
ARCHITECTURE untitled OF Comparator1 IS
BEGIN
 
 vhdl_Comparator1 : PROCESS(tag, tag0_out)
 
   BEGIN
 
   IF (tag = tag0_out) then
       Comp_Out1 <= '1' after 5ns;
   Else
       Comp_Out1 <= '0' after 5ns;
   end IF;
 
   END PROCESS vhdl_Comparator1;
END untitled;

data0_untitled.vhd

-- hds header_start
--
-- VHDL Architecture MP2_2.Data0.untitled
--
-- Created:
--          by - skim41.stdt (glsn46.ews.uiuc.edu)
--          at - 18:37:38 10/15/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2_2;
USE MP2_2.LC3b_types.all;
 
ENTITY Data0 IS
   PORT( 
      Clk        : IN     std_logic;
      PMDataIn   : IN     LC3b_CacheLine64;
      WriteEn0   : IN     std_logic;
      index      : IN     LC3b_index4;
      CacheLine0 : OUT    LC3b_CacheLine64
   );
 
-- Declarations
 
END Data0 ;
 
-- hds interface_end
ARCHITECTURE untitled OF Data0 IS
     TYPE data_array IS array (0 to 15) of LC3b_CacheLine64;
     signal data_array0 : data_array;
BEGIN
 
   -------------------------------------------------------------------
   vhdl_Data0 : PROCESS (WriteEn0, index, PMDataIn) 
   -------------------------------------------------------------------
 
     variable int_address : integer;
 
   BEGIN
     int_address := to_integer(unsigned(index));
 
     If (WriteEn0 = '1') then
        data_array0(int_address) <= PMDataIn;
     end if;
 
     CacheLine0 <= data_array0(int_address) after 22ns;
 
     END PROCESS vhdl_Data0;
 
END untitled;

lru_bit_untitled.vhd

-- hds header_start
--
-- VHDL Architecture MP2_2.LRU_bit.untitled
--
-- Created:
--          by - skim41.stdt (glsn46.ews.uiuc.edu)
--          at - 16:34:01 10/15/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2_2;
USE MP2_2.LC3b_types.all;
 
ENTITY LRU_bit IS
   PORT( 
      Clk       : IN     std_logic;
      index     : IN     LC3b_index4;
      lrusel    : OUT    std_logic;
      Reset_L   : IN     std_logic;
      lruupdate : IN     std_logic;
      lruload   : IN     std_logic
   );
 
-- Declarations
 
END LRU_bit ;
 
-- hds interface_end
ARCHITECTURE untitled OF LRU_bit IS
BEGIN
 
   -------------------------------------------------------------------
   vhdl_LRU_bit : PROCESS (LRUupdate, LRUload, index, Reset_L) 
   -------------------------------------------------------------------
     TYPE LRU_array IS array (0 to 15) of std_logic;
     VARIABLE LRUvar : LRU_array;
     VARIABLE int_address : integer;
   BEGIN
     int_address := to_integer(unsigned(index));
 
     IF (RESET_L = '0') then
        For i in 15 downto 0 loop
           LRUvar(i) := '1';
        END loop;
 
     ELSif (LRUload = '1') then
        LRUvar(int_address) := LRUupdate;
     End if;
 
     LRUSel <= LRUvar(int_address) after 51ns;
 
     END PROCESS vhdl_LRU_bit;
 
 
END untitled;

memory_untitled.vhd

-- hds header_start
--
-- VHDL Entity MP2.Memory.interface
--
-- Created:
--          by - skim41.stdt (eesn14.ews.uiuc.edu)
--          at - 14:48:44 09/27/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
LIBRARY MP2;
USE MP2.LC3b_types.all;
 
ENTITY Memory IS
   PORT( 
      ADDRESS   : IN     LC3b_word;
      DATAOUT   : IN     LC3b_word;
      MREAD_L   : IN     std_logic;
      MWRITEH_L : IN     std_logic;
      MWRITEL_L : IN     std_logic;
      RESET_L   : IN     std_logic;
      clk       : IN     std_logic;
      DATAIN    : OUT    LC3b_word;
      MRESP_H   : OUT    std_logic
   );
 
-- Declarations
 
END Memory ;
 
-- hds interface_end
--
-- VHDL Architecture MP1.Memory.untitled
--
-- Created by Greg Muthler
-- ECE 312 MP2 Memory VHDL        
--
-- Generated by Mentor Graphics' Renoir(TM) 99.1 (Build 26)
--
ARCHITECTURE untitled OF Memory IS
BEGIN
 
   -------------------------------------------------------------------
   vhdl_memory : PROCESS (RESET_L, MREAD_L, MWRITEH_L, MWRITEL_L) 
   -------------------------------------------------------------------
     TYPE memory_array IS	array (0 to 4096) of LC3b_byte;
     VARIABLE mem : memory_array;
     VARIABLE int_address : integer;
   BEGIN
     int_address := to_integer(unsigned('0' &amp; ADDRESS(11 downto 1) &amp; '0'));
     IF RESET_L = '0' then
       MRESP_H <= '0';
 
-- Insert Memory vectors here
-- Example: mem(0) := To_stdlogicvector(X"00");
 
	mem(0) := To_stdlogicvector(X"65");
	mem(1) := To_stdlogicvector(X"E0");
	mem(2) := To_stdlogicvector(X"00");
	mem(3) := To_stdlogicvector(X"62");
	mem(4) := To_stdlogicvector(X"01");
	mem(5) := To_stdlogicvector(X"64");
	mem(6) := To_stdlogicvector(X"02");
	mem(7) := To_stdlogicvector(X"6E");
	mem(8) := To_stdlogicvector(X"87");
	mem(9) := To_stdlogicvector(X"12");
	mem(10) := To_stdlogicvector(X"7E");
	mem(11) := To_stdlogicvector(X"16");
	mem(12) := To_stdlogicvector(X"43");
	mem(13) := To_stdlogicvector(X"12");
	mem(14) := To_stdlogicvector(X"41");
	mem(15) := To_stdlogicvector(X"12");
	mem(16) := To_stdlogicvector(X"0F");
	mem(17) := To_stdlogicvector(X"72");
	mem(18) := To_stdlogicvector(X"03");
	mem(19) := To_stdlogicvector(X"62");
	mem(20) := To_stdlogicvector(X"04");
	mem(21) := To_stdlogicvector(X"64");
	mem(22) := To_stdlogicvector(X"42");
	mem(23) := To_stdlogicvector(X"5C");
	mem(24) := To_stdlogicvector(X"AA");
	mem(25) := To_stdlogicvector(X"5B");
	mem(26) := To_stdlogicvector(X"10");
	mem(27) := To_stdlogicvector(X"7A");
	mem(28) := To_stdlogicvector(X"05");
	mem(29) := To_stdlogicvector(X"6E");
	mem(30) := To_stdlogicvector(X"FF");
	mem(31) := To_stdlogicvector(X"9F");
	mem(32) := To_stdlogicvector(X"11");
	mem(33) := To_stdlogicvector(X"7E");
	mem(34) := To_stdlogicvector(X"09");
	mem(35) := To_stdlogicvector(X"62");
	mem(36) := To_stdlogicvector(X"64");
	mem(37) := To_stdlogicvector(X"D4");
	mem(38) := To_stdlogicvector(X"52");
	mem(39) := To_stdlogicvector(X"D6");
	mem(40) := To_stdlogicvector(X"A1");
	mem(41) := To_stdlogicvector(X"D4");
	mem(42) := To_stdlogicvector(X"D1");
	mem(43) := To_stdlogicvector(X"D6");
	mem(44) := To_stdlogicvector(X"83");
	mem(45) := To_stdlogicvector(X"14");
	mem(46) := To_stdlogicvector(X"A1");
	mem(47) := To_stdlogicvector(X"14");
	mem(48) := To_stdlogicvector(X"73");
	mem(49) := To_stdlogicvector(X"D8");
	mem(50) := To_stdlogicvector(X"0A");
	mem(51) := To_stdlogicvector(X"62");
	mem(52) := To_stdlogicvector(X"76");
	mem(53) := To_stdlogicvector(X"DA");
	mem(54) := To_stdlogicvector(X"12");
	mem(55) := To_stdlogicvector(X"74");
	mem(56) := To_stdlogicvector(X"13");
	mem(57) := To_stdlogicvector(X"78");
	mem(58) := To_stdlogicvector(X"14");
	mem(59) := To_stdlogicvector(X"7A");
	mem(60) := To_stdlogicvector(X"5C");
	mem(61) := To_stdlogicvector(X"E2");
	mem(62) := To_stdlogicvector(X"16");
	mem(63) := To_stdlogicvector(X"72");
	mem(64) := To_stdlogicvector(X"6B");
	mem(65) := To_stdlogicvector(X"1B");
	mem(66) := To_stdlogicvector(X"16");
	mem(67) := To_stdlogicvector(X"BA");
	mem(68) := To_stdlogicvector(X"07");
	mem(69) := To_stdlogicvector(X"62");
	mem(70) := To_stdlogicvector(X"06");
	mem(71) := To_stdlogicvector(X"64");
	mem(72) := To_stdlogicvector(X"E0");
	mem(73) := To_stdlogicvector(X"56");
	mem(74) := To_stdlogicvector(X"A5");
	mem(75) := To_stdlogicvector(X"14");
	mem(76) := To_stdlogicvector(X"7F");
	mem(77) := To_stdlogicvector(X"12");
	mem(78) := To_stdlogicvector(X"FD");
	mem(79) := To_stdlogicvector(X"03");
	mem(80) := To_stdlogicvector(X"67");
	mem(81) := To_stdlogicvector(X"12");
	mem(82) := To_stdlogicvector(X"BA");
	mem(83) := To_stdlogicvector(X"14");
	mem(84) := To_stdlogicvector(X"FD");
	mem(85) := To_stdlogicvector(X"03");
	mem(86) := To_stdlogicvector(X"F9");
	mem(87) := To_stdlogicvector(X"05");
	mem(88) := To_stdlogicvector(X"01");
	mem(89) := To_stdlogicvector(X"08");
	mem(90) := To_stdlogicvector(X"0D");
	mem(91) := To_stdlogicvector(X"64");
	mem(92) := To_stdlogicvector(X"81");
	mem(93) := To_stdlogicvector(X"14");
	mem(94) := To_stdlogicvector(X"16");
	mem(95) := To_stdlogicvector(X"74");
	mem(96) := To_stdlogicvector(X"00");
	mem(97) := To_stdlogicvector(X"6C");
	mem(98) := To_stdlogicvector(X"2D");
	mem(99) := To_stdlogicvector(X"48");
	mem(100) := To_stdlogicvector(X"17");
	mem(101) := To_stdlogicvector(X"7C");
	mem(102) := To_stdlogicvector(X"60");
	mem(103) := To_stdlogicvector(X"5B");
	mem(104) := To_stdlogicvector(X"02");
	mem(105) := To_stdlogicvector(X"E6");
	mem(106) := To_stdlogicvector(X"C0");
	mem(107) := To_stdlogicvector(X"C0");
	mem(108) := To_stdlogicvector(X"08");
	mem(109) := To_stdlogicvector(X"6A");
	mem(110) := To_stdlogicvector(X"66");
	mem(111) := To_stdlogicvector(X"1B");
	mem(112) := To_stdlogicvector(X"18");
	mem(113) := To_stdlogicvector(X"7A");
	mem(114) := To_stdlogicvector(X"08");
	mem(115) := To_stdlogicvector(X"6A");
	mem(116) := To_stdlogicvector(X"87");
	mem(117) := To_stdlogicvector(X"F0");
	mem(118) := To_stdlogicvector(X"19");
	mem(119) := To_stdlogicvector(X"7A");
	mem(120) := To_stdlogicvector(X"29");
	mem(121) := To_stdlogicvector(X"E2");
	mem(122) := To_stdlogicvector(X"61");
	mem(123) := To_stdlogicvector(X"12");
	mem(124) := To_stdlogicvector(X"16");
	mem(125) := To_stdlogicvector(X"24");
	mem(126) := To_stdlogicvector(X"56");
	mem(127) := To_stdlogicvector(X"26");
	mem(128) := To_stdlogicvector(X"C2");
	mem(129) := To_stdlogicvector(X"18");
	mem(130) := To_stdlogicvector(X"1A");
	mem(131) := To_stdlogicvector(X"78");
	mem(132) := To_stdlogicvector(X"A1");
	mem(133) := To_stdlogicvector(X"14");
	mem(134) := To_stdlogicvector(X"FE");
	mem(135) := To_stdlogicvector(X"16");
	mem(136) := To_stdlogicvector(X"40");
	mem(137) := To_stdlogicvector(X"E2");
	mem(138) := To_stdlogicvector(X"79");
	mem(139) := To_stdlogicvector(X"34");
	mem(140) := To_stdlogicvector(X"78");
	mem(141) := To_stdlogicvector(X"36");
	mem(142) := To_stdlogicvector(X"1B");
	mem(143) := To_stdlogicvector(X"68");
	mem(144) := To_stdlogicvector(X"1A");
	mem(145) := To_stdlogicvector(X"78");
	mem(146) := To_stdlogicvector(X"2A");
	mem(147) := To_stdlogicvector(X"E6");
	mem(148) := To_stdlogicvector(X"1D");
	mem(149) := To_stdlogicvector(X"76");
	mem(150) := To_stdlogicvector(X"1D");
	mem(151) := To_stdlogicvector(X"A6");
	mem(152) := To_stdlogicvector(X"1C");
	mem(153) := To_stdlogicvector(X"76");
	mem(154) := To_stdlogicvector(X"FF");
	mem(155) := To_stdlogicvector(X"E9");
	mem(156) := To_stdlogicvector(X"05");
	mem(157) := To_stdlogicvector(X"65");
	mem(158) := To_stdlogicvector(X"A3");
	mem(159) := To_stdlogicvector(X"14");
	mem(160) := To_stdlogicvector(X"60");
	mem(161) := To_stdlogicvector(X"52");
	mem(162) := To_stdlogicvector(X"05");
	mem(163) := To_stdlogicvector(X"75");
	mem(164) := To_stdlogicvector(X"69");
	mem(165) := To_stdlogicvector(X"12");
	mem(166) := To_stdlogicvector(X"1E");
	mem(167) := To_stdlogicvector(X"72");
	mem(168) := To_stdlogicvector(X"21");
	mem(169) := To_stdlogicvector(X"12");
	mem(170) := To_stdlogicvector(X"4B");
	mem(171) := To_stdlogicvector(X"66");
	mem(172) := To_stdlogicvector(X"2E");
	mem(173) := To_stdlogicvector(X"EC");
	mem(174) := To_stdlogicvector(X"80");
	mem(175) := To_stdlogicvector(X"77");
	mem(176) := To_stdlogicvector(X"0B");
	mem(177) := To_stdlogicvector(X"62");
	mem(178) := To_stdlogicvector(X"07");
	mem(179) := To_stdlogicvector(X"06");
	mem(180) := To_stdlogicvector(X"08");
	mem(181) := To_stdlogicvector(X"62");
	mem(182) := To_stdlogicvector(X"2F");
	mem(183) := To_stdlogicvector(X"E4");
	mem(184) := To_stdlogicvector(X"80");
	mem(185) := To_stdlogicvector(X"40");
	mem(186) := To_stdlogicvector(X"81");
	mem(187) := To_stdlogicvector(X"73");
	mem(188) := To_stdlogicvector(X"FF");
	mem(189) := To_stdlogicvector(X"0F");
	mem(190) := To_stdlogicvector(X"FF");
	mem(191) := To_stdlogicvector(X"9D");
	mem(192) := To_stdlogicvector(X"C0");
	mem(193) := To_stdlogicvector(X"C1");
	mem(194) := To_stdlogicvector(X"08");
	mem(195) := To_stdlogicvector(X"62");
	mem(196) := To_stdlogicvector(X"06");
	mem(197) := To_stdlogicvector(X"22");
	mem(198) := To_stdlogicvector(X"08");
	mem(199) := To_stdlogicvector(X"24");
	mem(200) := To_stdlogicvector(X"06");
	mem(201) := To_stdlogicvector(X"66");
	mem(202) := To_stdlogicvector(X"00");
	mem(203) := To_stdlogicvector(X"68");
	mem(204) := To_stdlogicvector(X"00");
	mem(205) := To_stdlogicvector(X"00");
	mem(206) := To_stdlogicvector(X"70");
	mem(207) := To_stdlogicvector(X"00");
	mem(208) := To_stdlogicvector(X"0A");
	mem(209) := To_stdlogicvector(X"00");
	mem(210) := To_stdlogicvector(X"63");
	mem(211) := To_stdlogicvector(X"00");
	mem(212) := To_stdlogicvector(X"52");
	mem(213) := To_stdlogicvector(X"00");
	mem(214) := To_stdlogicvector(X"C7");
	mem(215) := To_stdlogicvector(X"BA");
	mem(216) := To_stdlogicvector(X"07");
	mem(217) := To_stdlogicvector(X"00");
	mem(218) := To_stdlogicvector(X"03");
	mem(219) := To_stdlogicvector(X"00");
	mem(220) := To_stdlogicvector(X"AD");
	mem(221) := To_stdlogicvector(X"0B");
	mem(222) := To_stdlogicvector(X"0D");
	mem(223) := To_stdlogicvector(X"0D");
	mem(224) := To_stdlogicvector(X"04");
	mem(225) := To_stdlogicvector(X"90");
	mem(226) := To_stdlogicvector(X"86");
	mem(227) := To_stdlogicvector(X"AE");
	mem(228) := To_stdlogicvector(X"60");
	mem(229) := To_stdlogicvector(X"54");
	mem(230) := To_stdlogicvector(X"05");
	mem(231) := To_stdlogicvector(X"00");
	mem(232) := To_stdlogicvector(X"66");
	mem(233) := To_stdlogicvector(X"00");
	mem(234) := To_stdlogicvector(X"00");
	mem(235) := To_stdlogicvector(X"00");
	mem(236) := To_stdlogicvector(X"00");
	mem(237) := To_stdlogicvector(X"00");
	mem(238) := To_stdlogicvector(X"00");
	mem(239) := To_stdlogicvector(X"00");
	mem(240) := To_stdlogicvector(X"00");
	mem(241) := To_stdlogicvector(X"00");
	mem(242) := To_stdlogicvector(X"00");
	mem(243) := To_stdlogicvector(X"00");
	mem(244) := To_stdlogicvector(X"00");
	mem(245) := To_stdlogicvector(X"00");
	mem(246) := To_stdlogicvector(X"00");
	mem(247) := To_stdlogicvector(X"00");
	mem(248) := To_stdlogicvector(X"00");
	mem(249) := To_stdlogicvector(X"00");
	mem(250) := To_stdlogicvector(X"00");
	mem(251) := To_stdlogicvector(X"00");
	mem(252) := To_stdlogicvector(X"00");
	mem(253) := To_stdlogicvector(X"00");
	mem(254) := To_stdlogicvector(X"00");
	mem(255) := To_stdlogicvector(X"00");
	mem(256) := To_stdlogicvector(X"00");
	mem(257) := To_stdlogicvector(X"00");
	mem(258) := To_stdlogicvector(X"00");
	mem(259) := To_stdlogicvector(X"00");
	mem(260) := To_stdlogicvector(X"00");
	mem(261) := To_stdlogicvector(X"00");
	mem(262) := To_stdlogicvector(X"00");
	mem(263) := To_stdlogicvector(X"00");
	mem(264) := To_stdlogicvector(X"00");
	mem(265) := To_stdlogicvector(X"00");
	mem(266) := To_stdlogicvector(X"00");
	mem(267) := To_stdlogicvector(X"00");
	mem(268) := To_stdlogicvector(X"00");
	mem(269) := To_stdlogicvector(X"00");
	mem(270) := To_stdlogicvector(X"10");
	mem(271) := To_stdlogicvector(X"01");
	mem(272) := To_stdlogicvector(X"0B");
	mem(273) := To_stdlogicvector(X"6A");
	mem(274) := To_stdlogicvector(X"7F");
	mem(275) := To_stdlogicvector(X"9B");
	mem(276) := To_stdlogicvector(X"C0");
	mem(277) := To_stdlogicvector(X"C1");
	mem(278) := To_stdlogicvector(X"0C");
	mem(279) := To_stdlogicvector(X"66");
	mem(280) := To_stdlogicvector(X"43");
	mem(281) := To_stdlogicvector(X"12");
	mem(282) := To_stdlogicvector(X"C0");
	mem(283) := To_stdlogicvector(X"C1");
	mem(284) := To_stdlogicvector(X"00");
	mem(285) := To_stdlogicvector(X"00");
 
-- Stop.
 
     ELSE
       IF ((int_address >= 0) and (int_address <= 4096)) THEN
         IF (MREAD_L = '0' and MWRITEL_L = '1' and MWRITEH_L = '1') THEN
             DATAIN(7 downto 0) <= mem(int_address) after 500 ns;             
             DATAIN(15 downto 8) <= mem(int_address + 1) after 500 ns;             
 
             MRESP_H <= '1' after 500 ns, '0' after 550 ns;
             -- You may change the '530ns' above to '500 + your clock cycle';
 
         ELSIF ((MWRITEL_L = '0' or MWRITEH_L = '0') and MREAD_L = '1') THEN
           if (MWRITEL_L = '0') then
             mem(int_address) := DATAOUT(7 downto 0);
           end if;
           if (MWRITEH_L = '0') then
             mem(int_address + 1) := DATAOUT(15 downto 8);
           end if;
           if (MWRITEH_L = '0' or MWRITEL_L = '0') then
 
             MRESP_H <= '1' after 500 ns, '0' after 550 ns;             
             -- You may change the '530ns' above to '500 + your clock cycle';
 
           end if;
         ELSE
           ASSERT false 
             REPORT "Memory Write"
             SEVERITY note;
         END IF;
       ELSE
         ASSERT false
           REPORT "Invalid address"
           SEVERITY warning;
       END IF;
     END IF;
   END PROCESS vhdl_memory;
 
END untitled;

regfile_untitled.vhd

-- hds header_start
--
-- VHDL Architecture MP1.RegFile.untitled
--
-- Created:
--          by - ykim29.stdt (eesn11.ews.uiuc.edu)
--          at - 18:17:38 09/08/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2;
USE MP2.LC3b_types.all;
 
ENTITY RegFile IS
   PORT( 
      RESET_L     : IN     std_logic;
      RFMuxout    : IN     LC3b_word;
      RegDest     : IN     LC3b_reg;
      RegWrite    : IN     std_logic;
      SrcB        : IN     LC3b_reg;
      StoreMuxout : IN     LC3b_reg;
      clk         : IN     std_logic;
      RFAout      : OUT    LC3b_word;
      rfbout      : OUT    LC3b_word
   );
 
-- Declarations
 
END RegFile ;
 
-- hds interface_end
 
ARCHITECTURE untitled OF RegFile IS
  type rammemory is array (7 downto 0) of LC3b_word;
  signal ram : rammemory;
BEGIN
   -------------------------------------------------------------------
  vhdl_regfile_read : PROCESS (ram, StoreMuxout, SrcB)
  -------------------------------------------------------------------
  variable raddr1 : integer range 0 to 7;
  variable raddr2 : integer range 0 to 7;
  BEGIN
    -- Read regfile Process.
    -- convert addresses to integers to use as an index into the array.
    raddr1 := to_Integer(unsigned('0' &amp; StoreMuxout));
    raddr2 := to_Integer(unsigned('0' &amp; SrcB));
    RFAout <= ram(raddr1) after delay_regfile_read;
    RFBout <= ram(raddr2) after delay_regfile_read;
  END PROCESS vhdl_regfile_read;
 
  -------------------------------------------------------------------
  vhdl_regfile_write: process(clk, RFMuxout, RegWrite, RegDest, RESET_L)
  -------------------------------------------------------------------
  variable waddr : integer range 0 to 7;
  BEGIN
    if (RESET_L = '0') then
      ram(0) <= "0000000000000000";
      ram(1) <= "0000000000000000";
      ram(2) <= "0000000000000000";
      ram(3) <= "0000000000000000";
      ram(4) <= "0000000000000000";
      ram(5) <= "0000000000000000";
      ram(6) <= "0000000000000000";
      ram(7) <= "0000000000000000";
    end if;
    -- convert address to integer
    waddr := to_Integer(unsigned('0' &amp; RegDest));
    if (clk'event and (clk = '1') and (clk'last_value = '0')) then
      if (RegWrite = '1') then
        ram(waddr) <= RFMuxout;
      end if;
    end if;
  END PROCESS vhdl_regfile_write;
 
END untitled;

shift_untitled.vhd

-- hds header_start
--
-- VHDL Architecture MP2.Shift.untitled
--
-- Created:
--          by - skim41.stdt (remsun2.ews.uiuc.edu)
--          at - 21:23:44 09/26/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2;
USE MP2.LC3b_types.all;
 
ENTITY Shift IS
   PORT( 
      Opcode   : IN     LC3b_opcode;
      RFAout   : IN     LC3b_word;
      clk      : IN     std_logic;
      imm4     : IN     LC3b_imm4;
      imm5     : IN     LC3b_imm5;
      index6   : IN     LC3b_index6;
      ShiftOut : OUT    LC3b_word
   );
 
-- Declarations
 
END Shift ;
 
-- hds interface_end
ARCHITECTURE untitled OF Shift IS
BEGIN
 
   vhdl_shift : PROCESS(imm5, imm4, index6, Opcode, RFAout)
        variable COUNT : integer;
	variable temp_shift : LC3b_word;
 
   BEGIN
     IF(Opcode = "1101") then
	IF(imm5(4) = '0') then
		ShiftOut <= std_logic_vector("sll"(unsigned(RFAout), to_integer(unsigned(imm4)))) after 2 ns;
	ELSIF(index6(5) = '0') then
		ShiftOut <= std_logic_vector("srl"(unsigned(RFAout), to_integer(unsigned(imm4)))) after 2 ns;
	ELSE
		COUNT := to_integer(unsigned(imm4(3 downto 0)));
		IF(imm4(3 downto 0) = "0000") then
			ShiftOut <= RFAout after 2 ns;
		ELSE
			temp_shift((15 - COUNT) downto 0) := RFAout(15 downto COUNT);
			temp_shift(15 downto (15 - COUNT + 1)) := (others => RFAout(15));
			ShiftOut <= temp_shift after 2 ns;
		end IF;
	end IF;
     ELSE
        ShiftOut <= RFAout after 2 ns;
     end IF;
   END PROCESS vhdl_shift;
END untitled;

zext_untitled.vhd

-- hds header_start
--
-- VHDL Architecture MP2.ZExt.untitled
--
-- Created:
--          by - skim41.stdt (eesn9.ews.uiuc.edu)
--          at - 02:12:53 09/24/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
 
 
LIBRARY MP2;
USE MP2.LC3b_types.all;
 
ENTITY ZExt IS
   PORT( 
      F        : IN     LC3b_word;
      Opcode   : IN     LC3b_opcode;
      clk      : IN     std_logic;
      RFMuxout : OUT    LC3b_word
   );
 
-- Declarations
 
END ZExt ;
 
-- hds interface_end
ARCHITECTURE untitled OF ZExt IS
BEGIN
  Zext : PROCESS (Opcode, F)
    ------------------------------
  BEGIN
 
   IF (Opcode = "0010" ) then
	RFMuxout <= ("00000000" &amp; F(7 downto 0)) after 1 ns;
   ELSE
        RFMuxout <= F after 1 ns;
   End IF;
  END PROCESS ZExt;
END untitled;

datapath_struct.vhd

-- hds header_start
--
-- VHDL Entity MP1.Datapath.interface
--
-- Created:
--          by - sye2.stdt (glsn10.ews.uiuc.edu)
--          at - 19:58:47 09/20/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
LIBRARY Debug;
USE Debug.LC3b_types.all;
 
ENTITY Datapath IS
   PORT( 
      ALUMuxSel : IN     std_logic;
      ALUop     : IN     LC3b_aluop;
      Clk       : IN     std_logic;
      DATAIN    : IN     LC3b_word;
      LoadIR    : IN     std_logic;
      LoadMAR   : IN     std_logic;
      LoadMDR   : IN     std_logic;
      LoadNZP   : IN     std_logic;
      LoadPC    : IN     std_logic;
      MARMuxSel : IN     std_logic;
      MDRMuxSel : IN     std_logic;
      PCMuxSel  : IN     std_logic;
      RESET_L   : IN     std_logic;
      RFMuxSel  : IN     std_logic;
      RegWrite  : IN     std_logic;
      StoreSR   : IN     std_logic;
      Address   : OUT    LC3b_word;
      CheckN    : OUT    std_logic;
      CheckP    : OUT    std_logic;
      CheckZ    : OUT    std_logic;
      DATAOUT   : OUT    LC3b_word;
      Opcode    : OUT    LC3b_opcode;
      bit5      : OUT    std_logic;
      n         : OUT    std_logic;
      p         : OUT    std_logic;
      z         : OUT    std_logic
   );
 
-- Declarations
 
END Datapath ;
 
-- hds interface_end
--
-- VHDL Architecture MP1.Datapath.struct
--
-- Created:
--          by - sye2.stdt (glsn10.ews.uiuc.edu)
--          at - 19:58:49 09/20/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
LIBRARY Debug;
USE Debug.LC3b_types.all;
 
LIBRARY MP1;
 
ARCHITECTURE struct OF Datapath IS
 
   -- Architecture declarations
 
   -- Internal signal declarations
   SIGNAL ADJ6out     : LC3b_word;
   SIGNAL ADJ9out     : LC3b_word;
   SIGNAL ALUMuxout   : LC3b_word;
   SIGNAL ALUout      : LC3b_word;
   SIGNAL BRaddout    : LC3b_word;
   SIGNAL GenCCout    : LC3b_cc;
   SIGNAL MARMuxout   : LC3b_word;
   SIGNAL MDRMuxout   : LC3b_word;
   SIGNAL MDRout      : LC3b_word;
   SIGNAL PCMuxout    : LC3b_word;
   SIGNAL PCPlus2out  : LC3b_word;
   SIGNAL PCout       : LC3b_word;
   SIGNAL RFAout      : LC3b_word;
   SIGNAL RFBout      : LC3b_word;
   SIGNAL RFMuxout    : LC3b_word;
   SIGNAL SrcA        : LC3b_reg;
   SIGNAL SrcB        : LC3b_reg;
   SIGNAL StoreMuxout : LC3b_reg;
   SIGNAL dest        : LC3b_reg;
   SIGNAL index6      : LC3b_index6;
   SIGNAL offset9     : LC3b_offset9;
 
 
   -- Component Declarations
   COMPONENT ADJ6
   PORT (
      Clk     : IN     std_logic ;
      index6  : IN     LC3b_index6 ;
      ADJ6out : OUT    LC3b_word 
   );
   END COMPONENT;
   COMPONENT ADJ9
   PORT (
      Clk     : IN     std_logic ;
      offset9 : IN     LC3b_offset9 ;
      ADJ9out : OUT    LC3b_word 
   );
   END COMPONENT;
   COMPONENT ALU
   PORT (
      ALUMuxout : IN     LC3b_word ;
      ALUop     : IN     LC3b_aluop ;
      Clk       : IN     std_logic ;
      RFAout    : IN     LC3b_word ;
      ALUout    : OUT    LC3b_word 
   );
   END COMPONENT;
   COMPONENT BRadd
   PORT (
      ADJ9out  : IN     LC3b_word ;
      Clk      : IN     std_logic ;
      PCout    : IN     LC3b_word ;
      BRaddout : OUT    LC3b_word 
   );
   END COMPONENT;
   COMPONENT GenCC
   PORT (
      Clk      : IN     std_logic ;
      RFMuxout : IN     LC3b_word ;
      GenCCout : OUT    LC3b_cc 
   );
   END COMPONENT;
   COMPONENT IR
   PORT (
      clk     : IN     std_logic ;
      loadir  : IN     std_logic ;
      mdrout  : IN     LC3b_word ;
      opcode  : OUT    LC3b_opcode ;
      srca    : OUT    LC3b_reg ;
      srcb    : OUT    LC3b_reg ;
      bit5    : OUT    std_logic ;
      dest    : OUT    LC3b_reg ;
      index6  : OUT    LC3b_index6 ;
      offset9 : OUT    LC3b_offset9 
   );
   END COMPONENT;
   COMPONENT NZP
   PORT (
      Clk      : IN     std_logic ;
      GenCCout : IN     LC3b_cc ;
      LoadNZP  : IN     std_logic ;
      n        : OUT    std_logic ;
      p        : OUT    std_logic ;
      z        : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT NZPsplit
   PORT (
      Clk    : IN     std_logic ;
      dest   : IN     LC3b_reg ;
      CheckN : OUT    std_logic ;
      CheckP : OUT    std_logic ;
      CheckZ : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT Plus2
   PORT (
      Clk        : IN     std_logic ;
      PCout      : IN     LC3b_word ;
      PCPlus2out : OUT    LC3b_word 
   );
   END COMPONENT;
   COMPONENT Reg16
   PORT (
      clk    : IN     std_logic ;
      input  : IN     LC3b_word ;
      load   : IN     std_logic ;
      reset  : IN     std_logic ;
      output : OUT    LC3b_word 
   );
   END COMPONENT;
   COMPONENT RegFile
   PORT (
      Clk         : IN     std_logic ;
      RESET_L     : IN     std_logic ;
      RFMuxout    : IN     LC3b_word ;
      RegWrite    : IN     std_logic ;
      SrcB        : IN     LC3b_reg ;
      StoreMuxout : IN     LC3b_reg ;
      dest        : IN     LC3b_reg ;
      RFAout      : OUT    LC3b_word ;
      RFBout      : OUT    LC3b_word 
   );
   END COMPONENT;
   COMPONENT SrcMux2
   PORT (
      a   : IN     LC3b_reg ;
      b   : IN     LC3b_reg ;
      sel : IN     std_logic ;
      f   : OUT    LC3b_reg 
   );
   END COMPONENT;
   COMPONENT WordMux2
   PORT (
      a   : IN     LC3b_word ;
      b   : IN     LC3b_word ;
      sel : IN     std_logic ;
      f   : OUT    LC3b_word 
   );
   END COMPONENT;
 
   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : ADJ6 USE ENTITY MP1.ADJ6;
   FOR ALL : ADJ9 USE ENTITY MP1.ADJ9;
   FOR ALL : ALU USE ENTITY MP1.ALU;
   FOR ALL : BRadd USE ENTITY MP1.BRadd;
   FOR ALL : GenCC USE ENTITY MP1.GenCC;
   FOR ALL : IR USE ENTITY MP1.IR;
   FOR ALL : NZP USE ENTITY MP1.NZP;
   FOR ALL : NZPsplit USE ENTITY MP1.NZPsplit;
   FOR ALL : Plus2 USE ENTITY MP1.Plus2;
   FOR ALL : Reg16 USE ENTITY MP1.Reg16;
   FOR ALL : RegFile USE ENTITY MP1.RegFile;
   FOR ALL : SrcMux2 USE ENTITY MP1.SrcMux2;
   FOR ALL : WordMux2 USE ENTITY MP1.WordMux2;
   -- pragma synthesis_on
 
 
BEGIN
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 1 eb1
   -- eb1 1
   DATAOUT<= MDRout;
 
   -- Instance port mappings.
   I0 : ADJ6
      PORT MAP (
         Clk     => Clk,
         index6  => index6,
         ADJ6out => ADJ6out
      );
   I9 : ADJ9
      PORT MAP (
         Clk     => Clk,
         offset9 => offset9,
         ADJ9out => ADJ9out
      );
   I5 : ALU
      PORT MAP (
         ALUMuxout => ALUMuxout,
         ALUop     => ALUop,
         Clk       => Clk,
         RFAout    => RFAout,
         ALUout    => ALUout
      );
   I7 : BRadd
      PORT MAP (
         ADJ9out  => ADJ9out,
         Clk      => Clk,
         PCout    => PCout,
         BRaddout => BRaddout
      );
   I6 : GenCC
      PORT MAP (
         Clk      => Clk,
         RFMuxout => RFMuxout,
         GenCCout => GenCCout
      );
   I1 : IR
      PORT MAP (
         Clk     => Clk,
         LoadIR  => LoadIR,
         MDRout  => MDRout,
         Opcode  => Opcode,
         SrcA    => SrcA,
         SrcB    => SrcB,
         bit5    => bit5,
         dest    => dest,
         index6  => index6,
         offset9 => offset9
      );
   I8 : NZP
      PORT MAP (
         Clk      => Clk,
         GenCCout => GenCCout,
         LoadNZP  => LoadNZP,
         n        => n,
         p        => p,
         z        => z
      );
   I12 : NZPsplit
      PORT MAP (
         Clk    => Clk,
         dest   => dest,
         CheckN => CheckN,
         CheckP => CheckP,
         CheckZ => CheckZ
      );
   I3 : Plus2
      PORT MAP (
         Clk        => Clk,
         PCout      => PCout,
         PCPlus2out => PCPlus2out
      );
   I2 : Reg16
      PORT MAP (
         clk    => Clk,
         input  => MDRMuxout,
         load   => LoadMDR,
         reset  => RESET_L,
         output => MDRout
      );
   MAR : Reg16
      PORT MAP (
         clk    => Clk,
         input  => MARMuxout,
         load   => LoadMAR,
         reset  => RESET_L,
         output => Address
      );
   I10 : Reg16
      PORT MAP (
         clk    => Clk,
         input  => PCMuxout,
         load   => LoadPC,
         reset  => RESET_L,
         output => PCout
      );
   I4 : RegFile
      PORT MAP (
         Clk         => Clk,
         RESET_L     => RESET_L,
         RFMuxout    => RFMuxout,
         RegWrite    => RegWrite,
         SrcB        => SrcB,
         StoreMuxout => StoreMuxout,
         dest        => dest,
         RFAout      => RFAout,
         RFBout      => RFBout
      );
   StoreMux : SrcMux2
      PORT MAP (
         a   => dest,
         b   => SrcA,
         sel => StoreSR,
         f   => StoreMuxout
      );
   I13 : WordMux2
      PORT MAP (
         A   => RFBout,
         B   => ADJ6out,
         Sel => ALUMuxSel,
         F   => ALUMuxout
      );
   MARMux : WordMux2
      PORT MAP (
         A   => PCout,
         B   => ALUout,
         Sel => MARMuxSel,
         F   => MARMuxout
      );
   PCMux : WordMux2
      PORT MAP (
         A   => PCPlus2out,
         B   => BRaddout,
         Sel => PCMuxSel,
         F   => PCMuxout
      );
   RFMux : WordMux2
      PORT MAP (
         A   => MDRout,
         B   => ALUout,
         Sel => RFMuxSel,
         F   => RFMuxout
      );
   MDRMux : WordMux2
      PORT MAP (
         A   => DATAIN,
         B   => ALUout,
         Sel => MDRMuxSel,
         F   => MDRMuxout
      );
 
END struct;

alu_untitled.vhd

-- hds header_start
--
-- VHDL Architecture ALU.untitled
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
LIBRARY Debug;
USE Debug.LC3b_types.all;
 
ENTITY ALU IS
   PORT( 
      ALUMuxout : IN     LC3b_word;
      ALUop     : IN     LC3b_aluop;
      Clk       : IN     std_logic;
      RFAout    : IN     LC3b_word;
      ALUout    : OUT    LC3b_word
   );
 
-- Declarations
 
END ALU ;
 
-- hds interface_end
ARCHITECTURE untitled OF ALU IS
BEGIN
  ----------------------------------------
  vhdl_ALU : PROCESS (RFAout, ALUMuxout, ALUop)
    ----------------------------------------
    variable Temp_ALUOut : LC3b_word;
  BEGIN
 
    -- check for ALU operation type, and execute
    case ALUop is
      when alu_add =>
        Temp_ALUOut := std_logic_vector(signed(RFAout) + signed(ALUMuxout));
      when alu_and =>
        Temp_ALUOut := (RFAout AND ALUMuxout);
      when alu_not =>
        Temp_ALUOut := (RFAout XOR "1111111111111111");
      when alu_pass =>
        Temp_ALUOut := (RFAout);
      when others =>
    end case;
 
    ALUout <= Temp_ALUOut after delay_ALU;
 
  END PROCESS vhdl_ALU;
 
END untitled;

adj6_untitled.vhd

-- hds header_start
--
-- VHDL Architecture ADJ6.untitled
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
LIBRARY Debug;
USE Debug.LC3b_types.all;
 
ENTITY ADJ6 IS
   PORT( 
      Clk     : IN     std_logic;
      index6  : IN     LC3b_index6;
      ADJ6out : OUT    LC3b_word
   );
 
-- Declarations
 
END ADJ6 ;
 
-- hds interface_end
ARCHITECTURE untitled OF ADJ6 IS
BEGIN
  ADJ6out <= index6(5)&amp;index6(5)&amp;index6(5)&amp;index6(5)&amp;index6(5)&amp;index6(5)&amp;index6(5)&amp;index6(5)&amp;index6(5)&amp;index6 &amp; '0';
END untitled;

bradd_untitled.vhd

-- hds header_start
--
-- VHDL Architecture BRadd.untitled
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
LIBRARY Debug;
USE Debug.LC3b_types.all;
 
ENTITY BRadd IS
   PORT( 
      ADJ9out  : IN     LC3b_word;
      Clk      : IN     std_logic;
      PCout    : IN     LC3b_word;
      BRaddout : OUT    LC3b_word
   );
 
-- Declarations
 
END BRadd ;
 
-- hds interface_end
ARCHITECTURE untitled OF BRadd IS
BEGIN
  vhdl_BRADD : process (PCout, ADJ9out)
  begin  -- process
 
    BRaddout <= std_logic_vector(signed(PCout) + signed(ADJ9out)) after delay_adder;
 
  end process;
END untitled;

gencc_untitled.vhd

-- hds header_start
--
-- VHDL Architecture GenCC.untitled
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
LIBRARY Debug;
USE Debug.LC3b_types.all;
 
ENTITY GenCC IS
   PORT( 
      Clk      : IN     std_logic;
      RFMuxout : IN     LC3b_word;
      GenCCout : OUT    LC3b_cc
   );
 
-- Declarations
 
END GenCC ;
 
-- hds interface_end
 
ARCHITECTURE untitled OF GenCC IS
BEGIN
  vhdl_GenCC : process (RFMuxout)
  begin    
	IF (RFMuxout = "0000000000000000") then
          GenCCout <= "010" after 6 ns;
        ELSIF (RFMuxout(15) = '1') then
          GenCCout <= "100" after 6 ns;
	ELSE
          GenCCout <= "001" after 6 ns;
        end IF;
  end process vhdl_GenCC;
END untitled;

ir_untitled.vhd

-- hds header_start
--
-- VHDL Architecture IR.untitled
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
LIBRARY Debug;
USE Debug.LC3b_types.all;
 
ENTITY IR IS
   PORT( 
      Clk     : IN     std_logic;
      LoadIR  : IN     std_logic;
      MDRout  : IN     LC3b_word;
      Opcode  : OUT    LC3b_opcode;
      SrcA    : OUT    LC3b_reg;
      SrcB    : OUT    LC3b_reg;
      bit5    : OUT    std_logic;
      dest    : OUT    LC3b_reg;
      index6  : OUT    LC3b_index6;
      offset9 : OUT    LC3b_offset9
   );
 
-- Declarations
 
END IR ;
 
-- hds interface_end
 
ARCHITECTURE untitled OF IR IS
  signal val_ir : LC3b_word;
BEGIN
  ------------------------------
  vhdl_Reg_IR : PROCESS (clk, LoadIR, MDRout)
    ------------------------------
  BEGIN
    if (clk'event and (clk = '1') and (clk'last_value = '0')) then
      if (LoadIR = '1') then
        val_ir <= MDRout after delay_reg;
      end if;
    end if;
  END PROCESS vhdl_Reg_IR;
 
  Opcode <= val_ir(15 downto 12);
  SrcA <= val_ir(8 downto 6);
  SrcB <= val_ir(2 downto 0);  -- was (8 downto 6)
  Dest <= val_ir(11 downto 9);
  offset9 <= val_ir(8 downto 0);
  index6 <= val_ir(5 downto 0);
  bit5 <= val_ir(5);
 
END untitled;

nzp_untitled.vhd

-- hds header_start
--
-- VHDL Architecture NZP.untitled
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
LIBRARY Debug;
USE Debug.LC3b_types.all;
 
ENTITY NZP IS
   PORT( 
      Clk      : IN     std_logic;
      GenCCout : IN     LC3b_cc;
      LoadNZP  : IN     std_logic;
      n        : OUT    std_logic;
      p        : OUT    std_logic;
      z        : OUT    std_logic
   );
 
-- Declarations
 
END NZP ;
 
-- hds interface_end
 
ARCHITECTURE untitled OF NZP IS
  signal pre_NZP : std_logic_vector (2 downto 0);
BEGIN
  ------------------------------
  vhdl_NZP : PROCESS (clk, GenCCout)
    ------------------------------
  BEGIN
    if (clk'event and (clk = '1') and (clk'last_value = '0')) then
      if (LoadNZP = '1') then
        pre_NZP <= GenCCout;
      end if;
    end if;
  END PROCESS vhdl_NZP;
 
  n <= pre_NZP(2) after delay_reg;
  z <= pre_NZP(1) after delay_reg;
  p <= pre_NZP(0) after delay_reg;
 
END untitled;

srcmux2_untitled.vhd

-- hds header_start
--
-- VHDL Architecture SrcMux2.untitled
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
LIBRARY Debug;
USE Debug.LC3b_types.all;
 
ENTITY SrcMux2 IS
   PORT( 
      a   : IN     LC3b_reg;
      b   : IN     LC3b_reg;
      sel : IN     std_logic;
      f   : OUT    LC3b_reg
   );
 
-- Declarations
 
END SrcMux2 ;
 
-- hds interface_end
ARCHITECTURE untitled OF SrcMux2 IS
BEGIN
	Process (A, B, Sel)
	variable state: LC3b_reg;
BEGIN
	case Sel is
		when '0' => state := A;
		when '1' => state := B;
		when others => state := (OTHERS => 'X');
	end case;
	F <= state after delay_MUX2;
END PROCESS;
END untitled;

ċ
Lc3b-processor-design-vhdl.zip
(1004k)
Hoon Kim,
Oct 9, 2011, 12:29 PM
Comments